The present invention relates to techniques for optimizing design of hard intellectual property blocks that are used for data transmission, and more particularly, to techniques for placing various portions of a data transmission block within a hard intellectual property block or in programmable logic to optimize the design.
The convergence of systems used in LAN, WAN, MAN, and SAN segments require new, interoperable communications technologies. Modular equipment must have flexible architectures that can support multiple protocols, including Ethernet for the LAN, SONET/SDH for the MAN/WAN, and Fiber Channel for the SAN.
System Packet Interface Level 4, Phase 2 (SPI4-2) is an electrical interface specification for complex communications systems. SPI4-2 allows communications systems to transmit multiple communications protocols using variable, high speed, data rates of up to 10 Giga bytes per second (Gbps), including Packet over SONET/SDH (POS), OC-192, Ethernet, Fast Ethernet, Gigabit Ethernet, 10 GbE, and 10G SAN. SPI4-2 enables developers to re-use hardware and software interface solutions from board to board, avoiding the necessity to build proprietary application specific integrated circuits (ASICs) for each communications protocol.
The SPI4-2 interface specification stipulates 16 bit wide transmitter and receiver data paths. The SPI4-2 interface specification also stipulates 2 bit wide FIFO status information is sent and received separately from the corresponding data path. The status information can be sent/received at either ⅛th of the SPI4.2 data rate, or at the SPI4.2 data rate (known as ‘full rate’).
Programmable logic devices (PLDs) are a type of programmable logic integrated circuit. Programmable logic integrated circuits can be configured to perform a variety of logical user functions. Programmable logic integrated circuits also include field programmable gate arrays (FPGAs), programmable logic arrays, configurable logic arrays, etc. Many of today's FPGAs have on-chip non-programmable application specific integrated circuit (ASIC) blocks, which are also called hard intellectual property (HIP) blocks.
SPI4-2 interface circuits align data that is received on 17 channels (16 data and 1 control). A SPI4-2 interface circuit can be implemented in programmable logic circuitry on a FPGA. SPI4-2 channel alignment functions typically consume hundreds of standard programmable logic elements on an FPGA; channel alignment is typically performed in programmable logic on a 128-bit or 64-bit wide data path, which requires numerous logic elements. Therefore, it would be desirable to reduce the amount of circuitry that is used to implement SPI4-2 channel alignment.
In addition, the most logic element conscious designs perform channel alignment serially, one channel at a time. The serial channel alignment methodology adds increased latency time before the channels have aligned, and the SPI4-2 receiver can declare synchronization. Therefore, it would be desirable to reduce the latency time needed to perform channel alignment for SPI4-2 interfaces.
Another problem facing FPGA designers is clock skew. In the past, circuit board designers typically synchronized clock signals that are driven to multiple integrated circuits on a board to reduce clock skew.
Another problem is that FPGA customers handle error conditions differently depending on the system requirements of their particular application. Therefore, it would also be desirable to provide flexible techniques for implementing error detection and error handling on FPGAs.
Within a single integrated circuit, clock signals are typically routed to circuit blocks on an integrated circuit through a clock network. Each node of a clock network is usually driven by different lengths of interconnect wires and driving buffers that introduce skew between clock signals at different nodes. Therefore, there is a need to reduce clock skew on programmable integrated circuits.